So it sounds like we’re designing the instruction pipeline for maximum parallelism for our task. I was surprised to learn that the first commercial FPGAs were available as early as the '80s. I can see how this would have been an extremely effective option before CUDA became available.
So it sounds like we’re designing the instruction pipeline for maximum parallelism for our task. I was surprised to learn that the first commercial FPGAs were available as early as the '80s. I can see how this would have been an extremely effective option before CUDA became available.